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2008 CDNLive MVP Case Study - New Technologies for 6 Gbps Serial Link Design and Simulation |
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2009 DesignCon Case Study - New Serial Link Simulation Process, 6 Gbps SAS |
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2010 DesignCon Paper Award Finalist - Simulation Techniques for 6+ Gbps Serial Links |
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3D S-Parameter Simulation in Allegro SI |
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A Process for Serial Link Signal Integrity Analysis - XrossTalk Magazine Article |
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Automating FPGA-Based PC Board Designs |
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Cadence Signal Integrity for Double Data Rate Interface |
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Cadence Signal Integrity for Double Data Rate Interface |
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How to Overcome Challenges in Designing a DDR2/DDR3 Memory System |
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Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Links Work Right Out of the Box |