可能感興趣的商品

  • DSP56852VFE

    廠商:Freescale

    類別:16位單片機(jī)

  • DSP56853FGE

    廠商:Freescale

    類別:16位單片機(jī)

  • DSP56854FGE

    廠商:Freescale

    類別:16位單片機(jī)

  • DSP56855BUE

    廠商:Freescale

    類別:16位單片機(jī)

  • DSP56857BUE

    廠商:Freescale

    類別:16位單片機(jī)

最近瀏覽過(guò)的商品

pic

Encounter Conformal Constraint Designer

廠商:
Cadence
類別:
邏輯設(shè)計(jì)
包裝:
-
封裝:
-
無(wú)鉛情況/ROHS:
-
描述:
Automates the validation and refi...

我要詢價(jià)我要收藏

  • 參數(shù)
  • 描述
  • 文檔
參數(shù) 數(shù)值
力特/littelfuse原裝現(xiàn)貨,可拆樣
請(qǐng)選擇文檔類型:
Brochure
文檔名稱 文檔類型 軟件 描述
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Cadence Encounter Digital IC Design Platform Brochure
Cadence Article
文檔名稱 文檔類型 軟件 描述
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Interview: Freescale's Alex Albuerne uses Encounter Timing System to Overcome Timing Challenges
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Interview: Low-Power Design and Verification using CPF
Conference Paper
文檔名稱 文檔類型 軟件 描述
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Automating Functional ECOs using Encounter Conformal Technology
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Functional ECO with Conformal Technology
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 How Not to "Wing It" on Your Timing Constraints
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Low-Power Verification Flow to Ease the Pain of Implementing MTCMOS-based MSMV Wireless Designs
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Real Design Challenges of Low-Power Physical Implementation
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Static Verification for Design Reuse and Quality
Datasheet
文檔名稱 文檔類型 軟件 描述
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Encounter Conformal Constraint Designer Datasheet
Demo
文檔名稱 文檔類型 軟件 描述
Encounter Conformal Constraint DesignerPDF下載 點(diǎn)擊下載 點(diǎn)擊下載 Cadence Encounter Digital IC Design Demo: Necessary and Absolute Signoff Analysis for 65/45nm Design