Description
The W641GG2JB is a 1G GDDR3 and speed involving -12/-14 status: Mass Production
Features
Density: 1Gbit
Pow e r su p p ly (V D D, VDDQ): 1.8V ± 0.1V
O r g aniz a t i on: 1 Chip Select x 8 ba n ks x 4M w o rds x 32 b its (1-CS mode) and 2 Chip Select x 8 ba n ks x 2M w o rds x 32 b i ts (2-CS m o de)
Eig h t inter n al ba n ks p e r Chip Select for c o ncurre n t op e ration
4n pr e f etch arch i t ecture: 128 b it p e r a r r a y R e ad or Write access
Double-data rate a r chitectu r e : two data t r ansfers per clock cycle
Sin g le en d ed interface for d a ta, a ddress and comma n d
Differenti a l c l ock i nputs CLK, CLK#
Comman d s e n tered on e a ch positive CLK e d ge
Sin g le en d ed Re a d stro b e ( R DQS) per byte, e d ge-a l ig n ed with Read d a ta
Single en d ed Write str o be (WDQS) p e r b yt e , center-a l ign e d with Write data
W rite da t a mask (D M ) function
DLL a lig n s DQ and RDQS tra n s i t i ons with CLK clock edg e s for Rea d s
Burst l e ngth (BL): 4 or 8
Seq u ential b u rst ty p e on l y
Programma b le CAS l a tency: 7 to 14
Programma b le Write late n cy: 3 to 7
Auto prech a r g e option for each b u rst access
Pseu d o o pen d r a in outp u ts with 4 0 W p u lld o wn, 4 0 W pul l u p
O D T : n o m. val u es of 60 W , 1 2 0 W or 2 4 0 W
Programma b le t e rm i nation a nd driver str e ngth offs e t s
Refresh cycles: 8192 cycles/32 m s
Auto-refresh and se l f -refresh mod e s
O D T and o u t p ut d r i ve stre n g th a u to-cal i b ration w i th extern a l r e sist o r ZQ pin ( 2 4 0 W )
Pr o grammab l e IO i n terf a ce i n clu d ing o n c h ip t e rm i nation (ODT)
tRAS l o ck o u t s u pport
Vendor ID for device identification
Mirror function with MF pin
Bou n dary Sc a n f u nct i on with SEN pin
? t W R pro g rammable for Writes with Auto-Precharge
Cal i b rated o u tp u t driv e . Act i ve termi n a tion sup p ort
S hort RAS to C A S timing for Writes
O p e rating case temp e r a t u re r a ng e : Tc a s e = 0 ° C to +85 ° C