參數(shù) | 數(shù)值 |
---|---|
Memory | 2048 |
Registers | 256 |
Max I/O Pins | 128 |
Usable Gates | 5K - 10K |
Speed | -2 |
F.max (MHz) | 100 MHz |
This 5,000 to 10,000-gate coprocessor is a fully PCI-compliant, SRAM-based FPGA with distributed 10-ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic® ability (partially or fully reconfigurable without loss of data), and automatic component generators. It has a 128 I/O count and supports a 5-V design. It can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. It is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform.