Virtex?-5 TXT FPGA平臺(tái)是賽靈思最新的創(chuàng)新成果，此平臺(tái)提供一種低風(fēng)險(xiǎn)的路徑，使電信設(shè)備制造商可以快速開發(fā)能適應(yīng)迅速發(fā)展的100G網(wǎng)絡(luò)市場(chǎng)的新產(chǎn)品原型，并快速將產(chǎn)品投入生產(chǎn)。這些FPGA是為數(shù)據(jù)中心中的布線器、交換機(jī)和高密度端口構(gòu)建高吞吐量（40Gbps、100Gbps以上）線卡的理想選擇。其高帶寬功能也能滿足視頻廣播和編輯設(shè)備、醫(yī)療影像系統(tǒng)及其他必須傳輸大量未經(jīng)壓縮的視頻數(shù)據(jù)的應(yīng)用的要求。
High-performance systems with double density advanced serial connectivity
Most advanced, high-performance, optimal-utilization,FPGA fabric
[1] Real 6-input look-up table (LUT) technology
[2] Dual 5-LUT option
[3] Improved reduced-hop routing
[4] 64-bit distributed RAM option
[5] SRL32/Dual SRL16 option
Powerful clock management tile (CMT) clocking
[1] Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
[2] PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs
[1] True dual-port RAM blocks
[2] Enhanced optional programmable FIFO logic
[3] Programmable
[4] Built-in optional error-correction circuitry
[5] Optionally program each block as two independent 18-Kbit blocks
High-performance parallel SelectIO technology
[1] 1.2 to 3.3V I/O Operation
[2] Source-synchronous interfacing using ChipSync? technology
[3] Digitally-controlled impedance (DCI) active termination
[4] Flexible fine-grained I/O banking
[5] High-speed memory interface support
Advanced DSP48E slices
[1] 25 x 18, two’s complement, multiplication
[2] Optional adder, subtracter, and accumulator
[3] Optional pipelining
[4] Optional bitwise logical functionality
[5] Dedicated cascade connections
Flexible configuration options
[1] SPI and Parallel FLASH interface
[2] Multi-bitstream support with dedicated fallback reconfiguration logic
[3] Auto bus width detection capability
System Monitoring capability on all devices
[1] On-chip/Off-chip thermal monitoring
[2] On-chip/Off-chip power supply monitoring
[3] JTAG access to all monitored quantities
Integrated Endpoint blocks for PCI Express Designs
[1] Compliant with the PCI Express Base Specification 1.1
[2] x1, x4, or x8 lane support per block
[3] Works in conjunction with RocketIO? transceivers
Tri-mode 10/100/1000 Mb/s Ethernet MACs
65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard or Pb-free package options