Virtex?-5 SXT FPGA針對DSP和存儲器密集型應用進行了優(yōu)化，是世界上首款采用1.0V三柵極氧化層工藝技術制造而成的65nm系列的引腳兼容成員。針對具有低功耗串行連接功能的DSP和存儲器密集型應用進行了優(yōu)化，整合了增強型DSP模塊，可以實現并行處理、最高的存儲器-邏輯比和用于實現最高I/O帶寬的低功耗串行收發(fā)器。
Virtex-5 SXT平臺為無線WIMAX以及監(jiān)控和廣播等高分辨率視頻等領域中的高性能數字信號處理應用提供了最高的DSP模塊和邏輯資源比。增強的DSP邏輯片(DSP48E)包括一個25x18位乘法器、一個48位第二級累加和算法運算單元以及一個可擴展到96位的48位輸出。更寬的數據路徑和輸出可支持更廣泛的動態(tài)范圍和更高的精度，同時 還優(yōu)化了對單精度浮點運算的支持，而所消耗的資源只有90nm FPGA的一半。
High-performance signal processing applications with advanced serial connectivity
Cross-platform compatibility
[1] SXT devices are footprint compatible in the same package using adjustable voltage regulators
Most advanced, high-performance, optimal-utilization, FPGA fabric
[2] Real 6-input look-up table (LUT) technology
[3] Dual 5-LUT option
[4] Improved reduced-hop routing
[5] 64-bit distributed RAM option
[6] SRL32/Dual SRL16 option
Powerful clock management tile (CMT) clocking
[1] Digital Clock Manager (DCM) blocks for zero delay mbuffering, frequency synthesis, and clock phase shifting
[2] PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs
[1] True dual-port RAM blocks
[2] Enhanced optional programmable FIFO logic Programmable
[3] True dual-port widths up to x36
[4] Simple dual-port widths up to x72
[5] Built-in optional error-correction circuitry
[6] Optionally program each block as two independent 18-Kbit blocks
High-performance parallel SelectIO technology
[1] 1.2 to 3.3V I/O Operation
[2] Source-synchronous interfacing using ChipSync? technology
[3] Digitally-controlled impedance (DCI) active termination
[4] Flexible fine-grained I/O banking
[5] High-speed memory interface support
Advanced DSP48E slices
[1] 25 x 18, two’s complement, multiplication
[2] Optional adder, subtracter, and accumulator
[3] Optional pipelining
[4] Optional bitwise logical functionality
[5] Dedicated cascade connections
Flexible configuration options
[1] SPI and Parallel FLASH interface
[2] Multi-bitstream support with dedicated fallback reconfiguration logic
[3] Auto bus width detection capability
System Monitoring capability on all devices
[1] On-chip/Off-chip thermal monitoring
[2] On-chip/Off-chip power supply monitoring
[3] JTAG access to all monitored quantities
Integrated Endpoint blocks for PCI Express Designs
[1] Compliant with the PCI Express Base Specification 1.1
[2] x1, x4, or x8 lane support per block
[3] Works in conjunction with RocketIO? transceivers
Tri-mode 10/100/1000 Mb/s Ethernet MACs
RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard or Pb-free package options