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XMEGA A4系列

所屬分類:
ATxmega系列單片機(jī)
目標(biāo)應(yīng)用:
工業(yè)控制
氣候控制
手持式電池
工廠自動(dòng)化
ZigBee
電動(dòng)工具
建筑控制
電機(jī)控制
空調(diào)
控制板
網(wǎng)絡(luò)
測(cè)量
白色家電
光纖接口
醫(yī)療應(yīng)用
  • 產(chǎn)品參數(shù)
  • 描述
  • 特性
The Atmel? AVR? XMEGA?A4 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A4 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA A4 devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 34 general purpose I/O lines, 16-bit Real Time Counter (RTC), five flexible 16-bit Timer/Counters with compare modes and PWM, five USARTs, two Two Wire Serial Interfaces (TWIs), two Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, one Twelve-channel, 12-bit ADC with optional differential input with programmable gain, one Two-channel 12-bit DAC, two analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
High-performance, Low-power 8/16-bit Atmel? AVR? XMEGA? Microcontroller
Non-volatile Program and Data Memories
   [1] 16 KB - 128 KB of In-System Self-Programmable Flash
   [2] 4 KB - 8 KB Boot Code Section with Independent Lock Bits
   [3] 1 KB - 2 KB EEPROM
   [4] 2 KB - 8 KB Internal SRAM
Peripheral Features
   [1] Four-channel DMA Controller with support for external requests
   [2] Eight-channel Event System
   [3] Five 16-bit Timer/Counters
   [4] Five USARTs
   [5] Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
   [6] Two SPIs (Serial Peripheral Interfaces) peripherals
   [7] AES and DES Crypto Engine
   [8] 16-bit Real Time Counter with Separate Oscillator
   [9] One Twelve-channel, 12-bit, 2 Msps Analog to Digital Converter
   [10] One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
   [11] Two Analog Comparators with Window compare function
   [12] External Interrupts on all General Purpose I/O pins
   [13] Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
   [1] Power-on Reset and Programmable Brown-out Detection
   [2] Internal and External Clock Options with PLL
   [3] Programmable Multi-level Interrupt Controller
   [4] Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
   [5] Advanced Programming, Test and Debugging Interfaces
PDI (Program and Debug Interface) for programming, test and debugging
I/O and Packages
   [1] 34 Programmable I/O Lines
   [2] 44 - lead TQFP
   [3] 44 - pad VQFN/QFN
   [4] 49 - ball VFBGA
Operating Voltage:1.6 – 3.6V
Speed performance
   [1] 12 MHz @ 1.6 – 3.6V
   [2] 32 MHz @ 2.7 – 3.6V